Memory controller

ABSTRACT

A memory controller includes an digitally programmable delay unit having a selectable delay time receiving a read-enable signal and outputting a delayed read-enable signal. The delay time is selected in response to an externally applied delay-control signal. A sampling unit in the memory controller outputs data received from a separate memory, in synchronization with the delayed enable signal. The delay time may be a multiple of the period of a clock signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. application Ser. No.12/272,100 filed on Nov. 17, 2008 which claims priority under 35 U.S.C.§119 to Korean Patent Application No. 10-2007-0116769 filed in theKorean Intellectual Property Office on Nov. 15, 2007, the disclosures ofwhich are incorporated by reference herein in their entireties.

BACKGROUND

1. Technical Field of the Invention

The invention relates to a memory controller, and more particularly, toa memory controller capable of precisely controlling data output time.

2. Description of the Related Art

In many computer systems, a memory controller is used to efficientlymanage the read and write transactions between a processor (orprocessors) and one or more random access memory (RAM) devices. Somememory controllers has a buffer (e.g., FIFO memory) that temporarilystores data to make data writing in a flash memory and data readingtherefrom smoother. To perform a data output (read) operationsynchronized with the operational clock (external clock) of a hostsystem, the memory controller may need to compensate for memory accesslatency. When the memory device detects a falling edge of a read-enablesignal RE, a read operation starts in the memory device. An activatedread-enable (RE) signal (e.g., transmitted through the memory controllerto the memory device) enables the memory device to output (read out)stored data, and the activated read-enable signal may then propagateback through the memory controller to indicate or control theavailability of valid read data. Read data may not be instantaneouslyavailable (output) from some memory devices at the same time that theread-enable signal is activated. The access time T_(REA) of a memorydepends upon the characteristics of the individual memory device. Somememory devices may have different memory access latencies T_(REA), suchthat read data may be output (available) later from some memory devicesthan from others. Thus, there is a need for a memory controller capableof variably delaying the propagation of a read-enable signal and readdata in the memory controller.

Delay lines are used within digital circuits such as board level systemsand integrated circuit (1C) devices, including field programmable gatearrays (FPGAs) and microprocessors, to control the timing of varioussignals in the digital circuits. A simple delay line receives an inputsignal on an input terminal and provides an output signal on an outputterminal, the output signal being a copy of the input signal delayed bya certain time period that is referred to as the delay D of the delayline. More complicated delay lines are tunable (e.g., digitallyprogrammable) so that delay D of the delay line can be adjusted.

SUMMARY

Connections between a memory controller formed on one integrated circuitand a memory device formed on a separate integrated circuit may producean unpredictable propagation delay and access time, which may produce aread error. In some memory devices, the access time may varydynamically, which may cause a read error. An aspect of the inventionprovides a memory controller that can prevent a read error generated dueto a variation in the access time during a data read so that the maximumperformance can be obtained during data reading.

According to an aspect of the invention, a memory controller comprises:an digitally programmable delay unit receiving a read-enable signal andoutputting a delayed read-enable signal having a variable delay timethat varies in response to an externally applied delay-control signal(e.g., a digital delay selection signal); and a sampling unit outputtingdata transmitted from a memory in synchronization with the enablesignal, wherein the delay time is a multiple of a period of a clocksignal.

The digital delay-control signal is a signal controlling the delay timethough the digitally programmable delay unit and is applied by a user,or by an external circuit.

The digitally programmable delay unit comprises a delay unit (e.g., amulti-tap delay block) receiving the read-enable signal, delaying areceived read-enable signal by an interval of a multiple of the periodof the clock signal, and outputting the delay signals having differentdelay times, and a switch unit selecting any one of the delay signalsand outputting the selected delay signal as the enable signal, inresponse to the digital delay-control signal.

The delay unit comprises a plurality of delay elements, each of whichdelays an input signal by an interval of a multiple of the period of theclock signal and outputs the delayed signal.

The switch unit comprises a delay selector outputting a switchingcontrol signal that determines the delay time according to the digitaldelay-control signal, and a switching device selectively outputting anyone of the delay signals in response to the switching control signal.

The delay unit comprises n number of delay cells in which an outputterminal of a k-th delay cell is connected to an input terminal of a(k+1)th delay cell, where k is a natural number that is not less than 1and not greater than n−1, and the first delay cell receives theread-enable signal, delays the received read-enable signal by a multipleof the period of the clock signal, and outputs a delayed signal insynchronization with the clock signal, where n is a natural number.

The switching device is formed of a multiplexer.

The sampling unit comprises a latch circuit that receives the enablesignal and data and outputs the data signal, in synchronization with theenable signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying figures provide a further understanding of the presentinvention, and are incorporated in and constitute a part of thisspecification. The drawings illustrate exemplary embodiments of thepresent invention and, together with the description, serve to explainprinciples of the present invention. In the figures:

FIG. 1 is a block diagram of a memory controller, according to anexemplary embodiment of the invention; and

FIG. 2 is a timing diagram for explaining the operation of the memorycontroller of FIG. 1.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1 is a block diagram of a memory controller 200 according to anexemplary embodiment of the invention. Referring to FIG. 1, the memorycontroller 200 includes a programmable delay unit 210 and a samplingunit 250.

The programmable delay unit 210 is a digitally programmable delay unitconfigured to delay an input read-enable signal RE by a variable delaytime, varying based upon an externally applied digital control signalCON_S, and outputs an enable signal EN. The variable delay time is amultiple of a period of a clock signal. Thus, when the period of a clocksignal CLK is period T, a delay time is nT, where “n” is a naturalnumber to be multiplied by period T.

The sampling unit 250 receives data DATA transmitted from a data source(e.g., a memory 270). When the enable signal EN is applied in anactivated state, the received data DATA is output as read data RDATA.The active enable signal EN may be predetermined as a logic high orlogic low level according to user settings.

The digital delay-control signal CON_S is a signal that controls thedelay time t_(d) (t_(d)=nT minus T, where n is a natural number selectedbased upon an externally applied digital delay-control signal CON_S. Ina preferred embodiment, n is an integer. For example, when the digitaldelay-control signal CON_S is input as an m-bit code, a code of “00001”makes the amount of delay 1T, a code of “00010” makes the amount ofdelay 2T, and a code of “00011” makes the amount of delay 3T.

The programmable delay unit 210 may include a d multi-tap delay block230 and a switch unit 220. The multi-tap delay block 230 receives theread-enable signal RE and repeatedly delays the input read-enable signalRE for a total delay time interval of a multiple (n times) of the periodof the clock signal CLK. For example, when the read-enable signal RE isinput at a time point t1 and the period of the clock signal CLK is T,the multi-tap delay block 230 outputs the read-enable signal RE at eachof time points t1+T, t1+2T, t1+3T, etc. and t1+nT.

Preferably, the multi-tap delay block 230 may include a plurality ofdelay elements e.g., clocked D-Q flip flops 231, 232, 233, and 234 thatare operated based on a clock signal CLK. Each of the delay elements(e.g., flops 231, 232, 233, and 234) may be a flip-flop, and the numbern of delay elements (e.g., the value of integer n) may be predeterminedby a designer considering the access time of the memory controller 200.The access time denotes the time period between the time point when thehost device requests data and the time point when effective data isavailable for use. Thus, the time point from when the read-enable signalRE is activated to the time point just before the memory 270 starts aread operation in response to the read-enable signal RE is the accesstime. When the access time is 10T (i.e., n=10), ten times of the periodof the maximum clock signal CLK, then ten delay elements may beprovided.

In the following description, for convenience of explanation, the delayelement 231, which first receives the read-enable signal RE, is referredto as the first delay element 231 and the delay elements sequentiallyarranged after the first delay element are referred to as the second,third, . . . , n-th delay element 232, 233, . . . , 23 n-th, where n isa natural number. Each of the n delay elements may implemented by anedge-triggered d-type (DQ) flip-flop. The D input of a D-type “positiveedge-triggered” flip-flop is sampled on the occurrence of the risingedge of the clock signal CLK (see, e.g., the rising edge of the CLOCKsignal at time point t1 in FIG. 2), and the sampled D input is latchedand transferred to the output Q. During all other conditions of thesignal CLK, the input D is ignored.

The first delay element (DQ flip-flop) 231 receives the read-enablesignal RE through an input terminal D via a first node N1, and isoperated in synchronization with the clock signal CLK. The first delaytime t_(dl) of the first delay element (DQ flip-flop) 231 is 1T. Asdescribed above, the time point synchronization is an interval of onecycle (period T) of the clock signal CLK. For example, when the firstdelay element 231 receives the read-enable signal RE at a time point t2,the read data RDATA is output from a terminal Q of the first delayelement (DQ flip-flop) 231 at a time point t2+T.

The second delay element 232 receives a data signal output from thefirst delay element 231 through its input terminal D at the time pointt2+T, the second delay element 232 outputs from its output terminal Q ata time point t2+2T. In general, the (k+1)th delay element receives asignal output from output terminal Q of the kth delay element at thetime point t2+kT, and the read data RDATA is output from the terminal Qof the (k+1)th delay element at a time point t2+(k+1)T, where k is anatural number that is not less than 1 and not greater than n.

That is, since each delay element outputs an input signal insynchronization with the clock signal CLK, each delay element has adelay time of 1T, which is one period of the clock signal CLK. Thesignal output by each of the delay elements 231, 232, 233, and 234through the terminal Q are input to the switch unit 220.

The switch unit 220 receives the inputs of signals output from the firstthrough nth delay elements 231, 232, . . . , 233, and 234 andselectively outputs one of the input signals. The switch unit 220 mayreceive the read-enable signal RE. Thus, the switch unit 220 selectivelyoutputs any one of the read-enable signal RE and the output signals ofthe first through nth delay elements 231, 232, . . . 233, and 234. Theswitch unit 220 may include a delay selector 222 and a switching device224.

The delay selector 222, in response to the digital delay-control signalCON_S, outputs a switching control signal corresponding to the digitaldelay-control signal CON_S. The switching control signal is a signal forcontrolling the amount of delay of the read-enable signal EN. Thus, theswitching control signal selects any one of the read-enable signal REand the output signals of the first, second, third, and fourth delayelements 231, 232, 233, and 234 so that the read-enable signal EN canhave a delay amount according to the digital delay-control signal CON_S.

The switching device 224, in response to the switching control signal,selects and outputs one of the read-enable signal RE and the outputsignals of the first, second, third, and fourth delay elements 231, 232,233, and 234, to a tenth node N10 that is at an output terminal of theswitching device 224. The switching device 224 may be a multiplexer(MUX).

The sampling unit 250 includes sampling devices such as flip-flops orlatches. The sampling unit 250, in response to the enable signal ENoutput from the switch unit 220, outputs the data DATA transmitted to atwelfth node N12 at an input terminal of the sampling unit 250, as theread data RDATA.

FIG. 2 is a timing diagram for explaining the operation of the memorycontroller 200 of FIG. 1. Referring to FIG. 2, a signal “CLOCK” maydenote the above-described clock signal CLK, and a signal “T_(CLK)”denotes one cycle (the period) of the clock signal CLK. In alternativeembodiments, the signal “CLOCK” may be produced by frequency-dividingthe above-described clock signal CLK In other embodiments, the signal“CLOCK” may be independent of the above-described clock signal CLK

When the read-enable input pin of the memory device 270 receives afalling edge of the read-enable signal RE, a read operation starts. At arising edge of the read-enable signal RE, the read operation stops.Thus, when the read-enable signal RE is in a logic low level, the memorycontroller 200 reads the data stored in the memory 270, and the readoperation is performed. The memory controller 200 transmits theread-enable signal RE to the memory 270. The propagation (delay) time ofthe read-enable signal RE transmitted from the memory controller 200 tothe memory 270 is T_(RE-TOF). Thus, T_(RE-TOF) is the time it takes forthe read-enable signal RE to be transmitted from the input node <a4> ofthe memory controller 200 at a time point t1 to the input node <a3> ofthe memory device at time point t2. Thus, the RE signal transmitted fromthe memory controller 200 to the memory 270 has the waveform as shown ofthe read-enable signal RE1 of FIG. 2.

The access time of the memory 270 is T_(REA). The time T_(DATA-TOF) isthe propagation (delay) time for transmitting the read data DATA1 outfrom the memory 270 into the memory controller 200. Thus, the timeinterval T_(DATA) _(—) _(TOF) is a propagation delay time that occurswhen the read data DATA1 is transmitted from data output node <a1> ofthe memory device 270 a time point t3 to the data input node <a> of thememory controller 200 a time point t4.

Thus, the time interval from the time point when the read-enable signalRE is a falling edge to the time point when the data read from thememory 270 is available (can be used by the memory controller 200) is atime interval between a time point t1 and a time point t4. Thus, thetime interval from the time point t1 to the time point t4 is the overallaccess time. The overall access time may not be an integer multiple ofthe period of the CLOCK signal.

Referring to a data DATA1, even when a data read operation starts at atime point t3, the read data can be output only after a predeterminedtime has elapsed. Thus, a set up time must be secured for all data readoperations, where the set up time signifies a time needed to stabilizedata. Also, a hold time must be secured. where the hold time is a timeto maintain the state of the read data for a predetermined period oftime, which is requested by the memory controller 200.

Referring to FIG. 2, the time from the time point t3 to a time point t5may be a sum of the set up time and the hold time. For reference, a timeTRC signifies a time needed for a predetermined unit of data to beoutput.

As shown in FIG. 2, at the time point t5, the read data DATA1 can beused by the memory controller 200. However, the time point t5 is aposition after the time point of <a2> t₃ when the read-enable signal REis raised. Accordingly, since data, for example, data DATA1, is outputat a time point when the read operation of the memory 270 is deactivatedby the read-enable signal RE, the requested data DATA is not properlytransmitted. That is, a data read error problem is generated.

In an exemplary embodiment of the invention shown in FIG. 1, theread-enable signal RE is delayed by a multiple of the cycle of the clocksignal CLK considering the access time. Thus, as shown in FIG. 2, as theread-enable signal RE is delayed by 3T of the overall read-enable signalRE, e.g., three cycles of the clock signal CLK, a problem that the readdata is not timely available can be prevented.

While the invention has been particularly shown and described withreference to exemplary embodiments thereof, it will be understood thatvarious changes in form and details may be made therein withoutdeparting from the spirit and scope of the following claims.

What is claimed is:
 1. A memory controller comprising: a programmabledelay unit configured to receive a periodic read-enable signal and tooutput a delayed periodic read-enable signal having a variable delaytime selected in response to a delay-control signal; and a sampling unitconfigured to output, in synchronization with the delayed periodicread-enable signal, data read out from a memory coupled to the memorycontroller, wherein the programmable delay unit generates a plurality ofdelay signals having different delay times by repeatedly delaying thereceived read-enable signal based on edges of a clock signal, andselectively outputs one of the delay signals as the delayed read-enablesignal.
 2. The memory controller of claim 1, wherein each of theplurality of delay signals is synchronized with the clock signal.
 3. Thememory controller of claim 1, wherein the delay-control signal is adigital signal controlling the delay time of the programmable delay unitand is supplied by a user.
 4. The memory controller of claim 1, whereinthe delay-control signal controls the delay time to approximately equalto an access time of the memory controller.
 5. The memory controller ofclaim 1, wherein the sampling unit comprises a latch circuit thatreceives the delayed read-enable signal and data and outputs the datasignal, in synchronization with the delayed read-enable signal.
 6. Thememory controller of claim 1, wherein the memory controller is formed ona first integrated circuit and the memory is formed on a separatedsecond integrated circuit.
 7. A memory controller, comprising: aprogrammable delay unit configured to receive a periodic read-enablesignal and to output a delayed periodic read-enable signal having avariable delay time selected in response to a delay-control signal,wherein the programmable delay unit comprises: a multi-tap delay blockreceiving the read-enable signal, and outputting a plurality of delaysignals having different delay times by repeatedly delaying the receivedread-enable signal based on a clock signal; and a switch unit configuredto select one of the plurality of delay signals and to output theselected delay signal as the delayed read-enable signal, in response tothe delay-control signal.
 8. The memory controller of claim 7, whereinthe multi-tap delay block comprises a plurality of delay cells, each ofwhich delays an input signal based on edges of the clock signal andoutputs the delayed signal.
 9. The memory controller of claim 8, whereineach of the delay cells is formed of a flip-flop.
 10. The memorycontroller of claim 7, wherein the multi-tap delay block comprises aplurality n of delay cells in which an output terminal of a k-th delaycell is connected to an input terminal of a (k+1)th delay cell, whereinn is a natural number, wherein k is a natural number that is not lessthan 1 and not greater than n−1, wherein the first one of the pluralityn of delay cells receives the read-enable signal, delays the receivedread-enable signal based on edges of the clock signal, and outputs adelayed read-enable signal in synchronization with the clock signal. 11.The memory controller of claim 10, wherein the k-th delay cell is formedof a positive edge-triggered flip-flop, wherein the (k+1)th delay cellis formed of a negative edge-triggered flip-flop.
 12. The memorycontroller of claim 10, wherein the multi-tap delay block furthercomprises a plurality m of delay cells in which an output terminal of ai-th delay cell is connected to an input terminal of a (i+1)th delaycell, wherein m is a natural number, wherein i is a natural number thatis not less than 1 and not greater than m−1, wherein the first one ofthe plurality m of delay cells receives the read-enable signal, whereineach of the plurality n of delay cells is formed of a positiveedge-triggered flip-flop, wherein each of the plurality m of delay cellsis formed of a negative edge-triggered flip-flop.
 13. The memorycontroller of claim 7, wherein the switch unit comprises: a delayselector configured to output a switching control signal that controlsthe delay time according to the delay-control signal; and a switchingdevice configured to select and output one of the delay signals inresponse to the switching control signal.
 14. The memory controller ofclaim 13, wherein the switching device is a multiplexer.